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XC2C256 CoolRunner-II CPLD
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DS094 (v2.6) October 1, 2004
Preliminary Product Specification
Features
* Optimized for 1.8V systems - As fast as 5.0 ns pin-to-pin delays - As low as 13 A quiescent current Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis. Refer to the CoolRunnerTM-II family data sheet for architecture description. - Multi-voltage I/O operation -- 1.5V to 3.3V Available in multiple package options - 100-pin VQFP with 80 user I/O - 144-pin TQFP with 118 user I/O - 132-ball CP (0.5mm) BGA with 106 user I/O - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 184 user I/O - Pb-free available for all packages Advanced system features - Fastest in system programming * 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management * DataGATE enable (DGE) signal control - Two separate output banks - RealDigital 100% CMOS product term generation - Flexible clocking modes * Optional DualEDGE triggered registers * Clock divider (divide by 2,4,6,8,10,12,14,16) * CoolCLOCK - Global signal options with macrocell control * Multiple global clocks with phase selection per macrocell * Multiple global output enables * Global set/reset - Advanced design security - PLA architecture * Superior pinout retention * 100% product term routability across function block - Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pull-up on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels * SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility - Hot pluggable
Description
The CoolRunnerTM-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.
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(c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is output banking. Two output banks are available on the CoolRunner-II 256 macrocell device that permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The CoolRunner-II 256 macrocell CPLD is I/O compatible with various I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
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for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL I/O standards make use of a VREF pin for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs Table 1: I/O Standards for XC2C256 Output VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Input VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Board Input Termination VREF Voltage VTT N/A N/A N/A N/A N/A 0.75 1.25 1.5 N/A N/A N/A N/A N/A 0.75 1.25 1.5
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance and low power operation.
I/O Types LVTTL LVCMOS33 LVCMOS25 LVCMOS18 1.5V I/O HSTL-1 SSTL2-1 SSTL3-1
For information on Vref, see XAPP399.
Supported I/O Standards
The CoolRunner-II 256 macrocell features LVCMOS, LVTTL, SSTL and HSTL I/O implementations. See Table 1
100
75
ICC (mA)
50
-6, -7
25
0 0 50 100 150 200 250 300
DS094_01_030102
Frequency (MHz)
Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical -6, -7 ICC (mA) Typical -5 ICC (mA)
Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block).
30 11.68
50 19.40
70 27.01
100 38.18
120 45.54
150 56.32
170 63.37
190 70.40
220 80.90
240 88.03
0.021
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol VCC VCCIO VJTAG(2) VAUX VIN(1) VTS(1) TSTG(3) TJ Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground Voltage applied to 3-state output Storage Temperature (ambient) Junction Temperature Value -0.5 to 2.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -65 to +150 +150 Units V V V V V V C C
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to -2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427.
Recommended Operating Conditions
Symbol VCC VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0C to +70C Industrial TA = -40C to +85C Min 1.7 1.7 3.0 2.3 1.7 1.4 1.7 Max 1.9 1.9 3.6 2.7 1.9 1.6 3.6 Units V V V V V V V
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation
VAUX
JTAG programming
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol ICCSB ICCSB ICCSB ICC ICC CJTAG CCLK CIO Parameter Standby current (-5) Standby current (-6, -7) Standby current (-7 industrial) Dynamic current (-6, -7) Dynamic current (-5) JTAG input capacitance Global clock input capacitance I/O capacitance Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz 10 12 10 33 54 150 300 410 27 Typical Max. Units A A A A mA mA mA pF pF pF
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
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Symbol IIL
(2) (2)
Parameter Input leakage current I/O High-Z leakage
Test Conditions VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V
Typical -1 -1
Max. 1 1
Units A A
IIH
Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block) tested at VCC= VCCIO = 1.9V 2. See Quality and Reliability section of the CoolRunner-II family data sheet
LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V Test Conditions Min. 3.0 2 -0.3 VCCIO - 0.4V VCCIO - 0.2V Max. 3.6 3.9 0.8 0.4 0.2 Units V V V V V V V
LVCMOS 2.5V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 2.3V IOH = -0.1 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V IOL = 0.1 mA, VCCIO = 2.3V Test Conditions Min. 2.3 1.7 -0.3 VCCIO - 0.4V VCCIO - 0.2V Max. 2.7 3.9 0.7 0.4 0.2 Units V V V V V V V
LVCMOS 1.8V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 1.7V IOH = -0.1 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V Test Conditions Min. 1.7 0.65 x VCCIO -0.3 VCCIO - 0.45 VCCIO - 0.2 Max. 1.9 3.9 0.35 x VCCIO 0.45 0.2 Units V V V V V V V
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
1.5V DC Voltage Specifications(1)
Symbol VCCIO VT+ VTVOH VOL High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 1.4V IOH = -0.1 mA, VCCIO = 1.4V IOL = 8 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V
Notes: 1. Hysteresis used on 1.5V inputs.
Parameter Input source voltage Input hysteresis threshold voltage
Test Conditions
Min. 1.4 0.5 x VCCIO 0.2 x VCCIO VCCIO - 0.45 VCCIO - 0.2 -
Max. 1.6 0.8 x VCCIO 0.5 x VCCIO 0.4 0.2
Units V V V V V V V
Schmitt Trigger Input DC Voltage Specifications
Symbol VCCIO VT+ VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO Max. 3.9 0.8 x VCCIO 0.5 x VCCIO Units V V V
SSTL2-1 DC Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V Test Conditions Min. 2.3 1.15 VREF - 0.04 VREF + 0.18 -0.3 VCCIO - 0.62 Typ 2.5 1.25 1.25 Max. 2.7 1.35 VREF + 0.04 3.9 VREF - 0.18 0.54 Units V V V V V V V
Notes: 1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
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XC2C256 CoolRunner-II CPLD
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SSTL3-1 DC Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V Test Conditions Min. 3.0 1.3 VREF - 0.05 VREF + 0.2 -0.3 VCCIO - 1.1 Typ 3.3 1.5 1.5 Max. 3.6 1.7 VREF + 0.05 VCCIO + 0.3 VREF - 0.2 0.7 Units V V V V V V V
Notes: 1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
HSTL1 DC Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V Test Conditions Min. 1.4 0.68 VREF + 0.1 -0.3 VCCIO - 0.4 Typ 1.5 0.75 VCCIO x 0.5 Max. 1.6 0.90 1.9 VREF - 0.1 0.4 Units V V V V V V V
Notes: 1. VREF should track the variations in VCCIO, also peak-to-peak AC noise on VREF may not exceed 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
-5(5) Symbol TPD1 TPD2 TSUD TSU1 TSU2 THD TH TCO FTOGGLE
(1) (2) (2)
-6 Min. 2.6 2.4 2.7 0 0 0.9 0.7 1.0 0.9 0.7 2.5 0 1.4 6.0 6.0 0 4.0 2.5 1.3 Max. 5.7 6.0 4.5 450 256 238 145 139 6.2 5.6 7.0 7.4 7.0 5.5 8.2 -
-7 Min. 3.0 2.8 3.3 0 0 1.7 1.5 2.0 1.2 1.0 3.1 0 2.2 7.5 7.5 0 6.0 3.5 2.0 Max . 6.7 7.5 6.0 300 152 141 114 108 7.3 7.0 8.0 9.9 8.1 7.6 9.0 Unit s ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter Propagation delay single p-term Propagation delay OR array Direct input register clock setup time Setup time (single p-term) Setup time (OR array) Direct input register hold time P-term hold time Clock to output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Direct input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low P-term pulse width High or Low Asynchronous preset/reset pulse width (High or Low) Set-up before DataGATE latch assertion Hold to DataGATE latch assertion DataGATE recovery to new data DataGATE low pulse width CDRST setup time before falling edge GCLK2
Min. 1.8 1.9 2.2 0 0 0.8 0.6 0.8 0.7 0.5 2.0 0 1.0 5.0 5.0 0 3.0 2.0 1.0
Max. 4.7 5.0 3.8 460 313 286 175 167 5.6 4.8 6.2 6.4 6.4 4.5 7.0 -
FSYSTEM1 FSYSTEM2 FEXT1 FEXT2
(3) (3)
TPSUD TPSU1 TPSU2 TPHD TPH TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC THEC TCW TPCW TAPRPW TDGSU TDGH TDGR TDGW TCDRSU
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
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-5(5) Symbol TCDRH TCONFIG
(4)
-6 Min. 0 150 Max. -
-7 Min. 0 150 Max . Unit s ns s
Parameter Hold time CDRST after falling edge GCLK2 Configuration time
Min. 0 150
Max. -
Notes: 1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more information). 2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per macrocell while FSYSTEM2 is through the OR array. 3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array. 4. Typical configuration current during TCONFIG is approximately 7.7 mA. 5. The -5 speed grade is Advanced Specification.
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
(
Internal Timing Parameters
-5(1) Symbol
Buffer Delays
-6 Max. 1.9 2.2 1.6 1.5 1.8 2.0 3.0 0.8 0.4 0.2 0.4 0.2 1.0 0 1.5 1.4 0.5 2.0 0.5 3.0 1.0 0 1.0 Min. 1.3 0 0.8 0 Max. 2.4 3.1 1.8 2.0 2.1 2.3 3.5 1.1 0.5 0.3 0.5 0.4 1.2 0 1.7 1.7 0.8 3.0 0.8 4.0 2.0 0 2.0 Min. 1.8 0 1.8 0 -
-7 Max. 2.6 3.9 2.7 3.5 3.0 2.6 4.0 1.4 1.1 0.5 0.7 0.7 1.5 0 3.0 2.5 1.0 4.0 1.0 5.0 3.0 0 4.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter(2) Input buffer delay Direct data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay Control term delay Single P-term delay adder Multiple P-term delay adder Input to output valid Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid Clock doubler delay Feedback delay Macrocell to global OE delay Standard input adder Hysteresis input adder Output adder Output slew rate adder Hysteresis input adder Output adder Output slew rate adder
Min. 1.2 0 0.6 0 -
TIN TDIN TGCK TGSR TGTS TOUT TEN
P-term Delays
TCT TLOGI1 TLOGI2 TPDI TSUI THI TECSU TECHO TCOI TAOI TCDBL TF TOEM TIN15 THYS15 TOUT15 TSLEW15 THYS18 TOUT18 TSLEW
Macrocell Delay
Feedback Delays
I/O Standard Time Adder Delays 1.5V I/O
I/O Standard Time Adder Delays 1.8V CMOS
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
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Internal Timing Parameters (Continued)
-5(1) Symbol TIN25 THYS25 TOUT25 TSLEW25 TIN33 THYS33 TOUT33 TSLEW33 SSTL2-1 Parameter(2) Standard input adder Hysteresis input adder Output adder Output slew rate adder Standard input adder Hysteresis input adder Output adder Output slew rate adder Input adder to TIN, TDIN, TGCK, TGSR,TGTS Output adder to TOUT SSTL3-1 Input adder to TIN, TDIN, TGCK, TGSR,TGTS Output adder to TOUT HSTL-1 Input adder to TIN, TDIN, TGCK, TGSR,TGTS Output adder to TOUT
Notes: 1. The -5 speed grade is Advanced Specification. 2. 1.5 ns input pin signal rise/fall.
-6 Max. 0.5 1.2 0.7 2.0 0.4 1.0 1.0 2.0 0.3 -0.5 0.3 -0.5 0.5 0 Min. -
-7 Max. 0.6 1.5 0.8 3.0 0.5 1.2 1.2 3.0 0.4 -0.5 0.4 -0.5 0.6 0 Min. -
Min. -
Max. 1.0 3.0 2.0 4.0 2.0 3.0 3.0 4.0 1.0 0.0 1.0 0.0 1.0 0
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
I/O Standard Time Adder Delays 2.5V CMOS
I/O Standard Time Adder Delays 3.3V CMOS/TTL
I/O Standard Time Adder Delays HSTL, SSTL
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Switching Characteristics
VCC = VCCIO = 1.8V, T = 25oC
5.5
AC Test Circuit
VCC R1
5.0
Device Under Test R2 CL
Test Point
4.5
TPD2 (ns)
Output Type
R1 268 275 188 112.5 150
R2 235 275 188 112.5 150
CL 35 pF 35 pF 35pF 35pF 35pF
4.0
LVTTL33 LVCMOS33 LVCMOS25
3.5
LVCMOS18 LVCMOS15
3.0 1 2 4 8 16
CL includes test fixtures and probe capacitance. 1.5 nsec maximum rise/fall times on inputs.
DS_ACT_08_14_02
Number of Outputs Switching
DS092_02_092302
Figure 3: AC Load Circuit
Figure 2: Derating Curve for TPD
60
3.3V
50
IO (Output Current mA)
40 1.8V 30
2.5V
Iol
20 1.5V 10
0 0 .5 1.0 1.5 2.0 2.5 3.0 3.5
VO (Output Volts)
XC256_VoIo_all_020703
Figure 4: Typical I/V Curve for XC2C256
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XC2C256 CoolRunner-II CPLD
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Pin Descriptions
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 I/O Bank
Pin Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 I/O Bank
1 1 1(GSR) 1 1 1 1 1 1 1 1 1 1 1 1 1 2(GTS2) 2 2(GTS3) 2 2(GTS0) 2 2 2 2 2 2 2(GTS1) 2 2 2 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
99 97 96 95 94 1 2 3 4 6 7 -
A3 B4 A4 C5 A1 B2 B1 C3 C2 C1 D2 D1
143 142 140 139 138 137 2 3 4 5 6 7 9 10 -
2 208 206 205 203 202 201 200 199 198 197 3 4 5 6 7 8 9 10 12 14 -
B3 B4 C4 A2 A3 A4 B5 A5 E8 B6 C7 D3 C3 E3 B2 D4 D2 E5 B1 E4 C1 E2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
93
B5 A5 C6
136 135 134 133
196 195 194 193 192 191
A6 D7 B7 E9 A7 D8 B8 C8 A8 E11 E10 F2 F3 G4 G3 F5 G5 H2 H4 H3 H1 H5
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
92 91 90 8 9 10 11 12 13 -
B6 A6 C7 B7 E3 E2 E1 F3 F2 F1 G1 -
132 131 11 12 13 14 15 16 17 18 -
189 188 187 186 185 15 16 17 18 19 20 21 22 23 25
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Pin Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 I/O Bank
Pin Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 I/O Bank
5 5 5 5(GCK1) 5 5(GCK0) 5 5 5 5 5 5 5 5 5 5 6 6 (CDRST) 6 6(GCK2) 6 6 6 6 6 6 6 6(DGE) 6 6 6 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
23
L3 L2 L1
33 32 31 30 28 34 35 38 39 40 41 42 43
49 48 47 46 45 44 43 41 40 39 38 50 51 54 55 56 57 58 60 61 62 63
R1 N4 N2 M3 P1 M2 L3 N1 L4 M1 L5 N3 P2 P4 P5 R2 T1 T2 N5 R4 M5 R5
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
19 18 17 16 15 14 32 33 34 35 36 37 -
J2 J1 H3 H2 H1 G3 G2 N4 M5 N5 P5 M6 N6 -
26 25 24 23 22 21 20 19 44 45 46 48 49 50 51 52 -
37 36 35 34 32 31 30 29 28 27 64 65 66 67 69 70 71 72 73 74 75 76
K4 L2 K3 L1 K5 K2 J4 K1 J3 J2 J5 J1 R6 N6 R3 M6 T3 P6 T4 P7 T5 N7 R7 M7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22 24 27 28 29 30
K3 K1 M1 M2 N2 P2 M3 N3 P3 M4
8 8 8 8 8 8 8 8 8 8 8 8 8
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XC2C256 CoolRunner-II CPLD
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Pin Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 I/O Bank
Pin Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 I/O Bank
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
78 79 80
C12 B12 A12
112 113 114
160 161 162 163 164
B13 B14 C13 A15 C12 B12 D13 A14 E13 A13 C11 A12 A16 B15 C14 G11 B16 D15 E14 C16 F14 F13 E15 G13
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
85 86 87 89 68 67 66 65 -
B10
-
173 174 175 178 179 180 182 183 184 145 144 143 142 140 139 138 137 136 135 134 -
B11 D11 A11 D10 B10 E12 F12 B9 C9 C10 A9 D9 F15 G14 E16 H12 F16 H16 G15 H13 G16 H14 H15 J12
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A10 C9 A8 B8 C8 F12 F13 F14 G12 G13 -
120 121 124 125 126 128 129 130 100 98 97 96 95 94 -
81 82 77 76 74 73 72 71 -
C11 B11 A11 C10 A13 B13 C13 C14 D12 D13 -
115 116 117 118 119 111 110 107 106 105 104 -
165 166 167 168 169 170 171 159 158 155 154 153 152 151
70 -
D14 E12 E13
103 102 101
150 149 148 147 146
14
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Pin Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 I/O Bank
Pin Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 I/O Bank
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
53 54 55 56 52 50 49 46 44 -
N13 N14 M12 M13 M14 L12 L13 P14 P12 M11 N11 P11 P10 P9
75 76 77 78 79 80 81 82 74 71 70 69 68 66 64 61
107 108 109 110 111 112 113 114 115 116 117 106 103 102 101 100 99 97 95 91
R15 T16 N14 R16 N15 M15 M13 P16 N16 L14 M14 P15 P14 P13 R13 N13 R14 T15 R12 N11 M11 N10
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
58 59 60 61 63 64 43 42 41 40 39 -
L14 K13 K14 J12 J13 H13 H12 M8 N8 P8 M7 N7 P6
83 85 86 87 88 91 92 60 59 58 57 56 54 53
118 119 120 121 122 123 125 126 127 128 131 90 89 88 87 86 85 84 83 82 80 78 77
L15 L13 M12 M16 K14 L16 K15 L12 K16 J14 J15 J13 P10 R10 T10 R9 N9 M8 T8 P8 R8 T7 N8 T6
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable.
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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15
XC2C256 CoolRunner-II CPLD
R
XC2C256 JTAG, Power/Ground, No Connect Pins and Total User I/O
Pin Type TCK TDI TDO TMS VAUX (JTAG supply voltage) Power internal (VCC) Power Bank 1 I/O (VCCIO1) Power Bank 2 I/O (VCCIO2) Ground VQ100 48 45 83 47 5 26, 57 20, 38, 51 88, 98 21, 25, 31, 62, 69, 75, 84, 100 CP132 M10 M9 B9 N10 D3 P1, K12, A2 J3, P7, G14, P13 A14, C4, A7 K2, N1, P4, N9, N12, J14, H14, E14, B14, A9, B3 TQ144 67 63 122 65 8 1, 37, 84 27, 55, 73, 93 109, 127, 141 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 PQ208 98 94 176 96 11 1, 53, 124 33, 59, 79, 92, 105, 132 26, 133, 157, 172, 181, 204 13, 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190, 207 FT256 P12 R11 A10 N12 F4 P3, K13, D12, D5 J6, K6, L7, L8, J11, K11, L10, L9 F7, F8, G6, H6, F10, F9, H11 F11, F6, G10, G7, G8, G9, H10, H7, H8, H9, J10, J7, J8, J9, K10, K7, K8, K9, L11, L6 A1, C2, E6, D1, E1, G2, F1, G1, M4, T9, P9, M9, M10, T11, T12, T13, P11, T14, J16, K12, D16, G12, C15, D14, D6, C6, E7, C5 184
No connects
-
-
Total user I/O
80
106
118
173
16
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
R
XC2C256 CoolRunner-II CPLD
Ordering Information
Commercia l (C) Part Number XC2C256-5VQ100C(2) XC2C256-6VQ100C XC2C256-7VQ100C XC2C256-5CP132C(2) XC2C256-6CP132C XC2C256-7CP132C XC2C256-5TQ144C(2) XC2C256-6TQ144C XC2C256-7TQ144C XC2C256-5PQ208C(2) XC2C256-6PQ208C XC2C256-7PQ208C XC2C256-5FT256C(2) XC2C256-6FT256C XC2C256-7FT256C XC2C256-5VQG100C(2) XC2C256-6VQG100C XC2C256-7VQG100C XC2C256-5CPG132C(2) XC2C256-6CPG132C XC2C256-7CPG132C XC2C256-5TQG144C(2) XC2C256-6TQG144C XC2C256-7TQG144C XC2C256-5PQG208C(2) Pin/Ball Spacing 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm JC JA (C/Watt) (C/Watt) 43.1 43.1 43.1 65.0 65.0 65.0 37.2 37.2 37.2 36.9 36.9 36.9 34.6 34.6 34.6 43.1 43.1 43.1 65.0 65.0 65.0 37.2 37.2 37.2 36.9 10.9 10.9 10.9 15.0 15.0 15.0 7.2 7.2 7.2 9.7 9.7 9.7 6.1 6.1 6.1 10.9 10.9 10.9 15.0 15.0 15.0 7.2 7.2 7.2 9.7 Package Type Very Thin Quad Flat Pack Very Thin Quad Flat Pack Very Thin Quad Flat Pack Chip Scale Package Chip Scale Package Chip Scale Package Thin Quad Flat Pack Thin Quad Flat Pack Thin Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin BGA Fine Pitch Thin BGA Fine Pitch Thin BGA Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Chip Scale Package; Pb-free Chip Scale Package; Pb-free Chip Scale Package; Pb-free Thin Quad Flat Pack; Pb-free Thin Quad Flat Pack; Pb-free Thin Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Package Body Dimensions 14mm x 14mm 14mm x 14mm 14mm x 14mm 8mm x 8mm 8mm x 8mm 8mm x 8mm 20mm x 20mm 20mm x 20mm 20mm x 20mm 28mm x 28mm 28mm x 28mm 28mm x 28mm 17mm x 17mm 17mm x 17mm 17mm x 17mm 14mm x 14mm 14mm x 14mm 14mm x 14mm 8mm x 8mm 8mm x 8mm 8mm x 8mm 20mm x 20mm 20mm x 20mm 20mm x 20mm 28mm x 28mm I/O 80 80 80 106 106 106 118 118 118 173 173 173 184 184 184 80 80 80 106 106 106 118 118 118 173 Industrial (I)(1) C C C C C C C C C C C C C C C C C C C C C C C C C
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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17
XC2C256 CoolRunner-II CPLD
R
Commercia l (C) Part Number XC2C256-6PQG208C XC2C256-7PQG208C XC2C256-5FTG256C(2) XC2C256-6FTG256C XC2C256-7FTG256C XC2C256-7VQ100I XC2C256-7CP132I XC2C256-7TQ144I XC2C256-7PQ208I XC2C256-7FT256I XC2C256-7VQG100I XC2C256-7CPG132I XC2C256-7TQG144I XC2C256-7PQG208I XC2C256-7FTG256I Pin/Ball Spacing 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm JC JA (C/Watt) (C/Watt) 36.9 36.9 34.6 34.6 34.6 43.1 65.0 37.2 36.9 34.6 43.1 65.0 37.2 36.9 34.6 9.7 9.7 6.1 6.1 6.1 10.9 15.0 7.2 9.7 6.1 10.9 15.0 7.2 9.7 6.1 Package Type Plastic Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch Thin BGA; Pb-free Very Thin Quad Flat Pack Chip Scale Package Thin Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin BGA Very Thin Quad Flat Pack; Pb-free Chip Scale Package; Pb-free Thin Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Fine Pitch Thin BGA; Pb-free Package Body Dimensions 28mm x 28mm 28mm x 28mm 17mm x 17mm 17mm x 17mm 17mm x 17mm 14mm x 14mm 8mm x 8mm 20mm x 20mm 28mm x 28mm 17mm x 17mm 14mm x 14mm 8mm x 8mm 20mm x 20mm 28mm x 28mm 17mm x 17mm I/O 173 173 184 184 184 80 106 118 173 184 80 106 118 173 184 Industrial (I)(1) C C C C C I I I I I I I I I I
Notes: 1. C = Commercial (TA = 0C to +70C); I = Industrial (TA = -40C to +85C) 2. Inquire with your local sales representative for availability of this part.
Standard Example: XC2C128 Device Speed Grade Package Type Number of Pins Temperature Range
-4 TQ
144
C
Pb-Free Example: XC2C128 Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range
-4 TQ
G
144
C
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
R
XC2C256 CoolRunner-II CPLD
Device Part Marking
R
Device Type Package Speed Operating Range
XC2Cxxx TQ144 7C
This line not related to device part number
Part marking for non-chip scale package
Figure 5: Sample Package with Part Marking
Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale packages by line are: * * * Line 1 = X (Xilinx logo) then truncated part number Line 2 = Not related to device part number Line 3 = Not related to device part number 1. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C5 = CP132, C6 = CPG132.
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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19
XC2C256 CoolRunner-II CPLD
R
20
VCC I/O(2) I/O(5) I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO1 I/O I/O I/O I/O I/O I/O TDI I/O TMS TCK I/O I/O
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O(1) I/O(1) I/O(1) I/O(1) VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 GND I/O(2) I/O(2) I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VCCIO2
I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O
GND I/O(3)
VQ100 Top View
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O VCCIO1
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - Data Gate
Figure 6: VQ100 Very Thin Quad Flat Pack
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
10
11
12
13
VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
P N M L K J H G F E D C B A
VCC GND
I/O(5) I/O(2)
I/O I/O
GND I/O
I/O I/O
I/O I/O
VCCIO1 I/O
I/O I/O
I/O GND
I/O TMS
I/O I/O
I/O GND
I/O I/O
I/O
I/O(4)
I/O
I/O
I/O
I/O
I/O
I/O
TDI
TCK
I/O
I/O
I/O
I/O
I/O(2)
I/O
I/O
I/O
I/O
GND
I/O(2)
VCC
I/O
I/O
I/O
VCCIO1
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
CP132 Bottom View
I/O
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VAUX
I/O
I/O
I/O
I/O(1)
I/O(1)
VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O(1)
I/O(1) VCC
GND I/O(3)
I/O I/O
I/O I/O
I/O I/O
I/O VCCIO2
I/O I/O
TDO GND
I/O I/O
I/O I/O
I/O I/O
GND VCCIO2
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
Figure 7: CP132 Chip Scale Package
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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14
1
2
3
4
5
6
7
8
9
21
XC2C256 CoolRunner-II CPLD
R
VCC I/O(1) I/O(1) I/O I/O(1) I/O(1) I/O VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 I/O GND I/O(2) I/O I/O(2) I/O I/O I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND I/O(3) I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2
TQ144 Top View
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCIO1 I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1
VCC I/O(2) I/O(5) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O
Figure 8: TQ144 Thin Quad Flat Pack
22
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VCCIO1 I/O I/O I/O I/O I/O I/O GND TDI I/O TMS I/O TCK I/O I/O I/O I/O GND
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
VCC I/O I/O(1) I/O I/O(1) I/O I/O(1) I/O I/O(1) I/O VAUX I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCCIO2 I/O I/O I/O I/O I/O I/O VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O(2) I/O I/O(2) I/O I/O I/O I/O I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
I/O GND I/O(3) I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2 I/O I/O I/O GND TDO I/O I/O I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2
PQ208 Top View
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
VCC I/O I/O(2) I/O I/O I/O(5) VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 GND TDI I/O TMS I/O TCK I/O I/O I/O I/O I/O GND
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO2 VCCIO1 I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
Figure 9: PQ208 Quad Flat Package
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XC2C256 CoolRunner-II CPLD
R
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
I/O I/O NC I/O I/O I/O NC I/O I/O I/O I/O I/O(2) I/O I/O(4) I/O I/O(5)
A B C D E F G H J K L M N P R T
I/O
I/O
I/O
I/O
I/O
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O(3)
I/O
I/O
NC
I/O
NC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
NC
VCC
I/O(1)
I/O(1)
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O(1)
I/O
I/O(1)
NC
I/O
I/O
I/O
I/O
I/O
GND
VCCIO2 VCCIO2 VCCIO2 VCCIO2
GND
I/O
VAUX
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
GND
GND
GND
GND
VCCIO2
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
VCCIO2
GND
GND
GND
GND
VCCIO2
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
VCCIO1
GND
GND
GND
GND
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
NC
VCCIO1
GND
GND
GND
GND
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCIO1 VCCIO1 VCCIO1 VCCIO1
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
NC
I/O(2)
I/O
I/O
I/O
I/O
I/O
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
NC
I/O
NC
I/O
I/O
I/O
I/O(2)
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT256 Bottom View
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
Figure 10: FT256 Fine Pitch Thin BGA
Additional Information
CoolRunner-II Datasheets and Application Notes Device Packages
24
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DS094 (v2.6) October 1, 2004 Preliminary Product Specification
1
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XC2C256 CoolRunner-II CPLD
Revision History
The following table shows the revision history for this document. Date 05/09/02 05/13/02 10/31/02 03/17/03 04/02/03 01/26/04 02/26/04 08/03/04 08/19/04 10/01/04 Version 1.0 1.1 1.2 2.0 2.1 2.2 2.3 2.4 2.5 2.6 Initial Xilinx release. Updated AC Electrical Characteristics and added new parameters. Corrected package user I/O, added Voltage Referenced DC tables. Added Characterization numbers for product release and device part marking Updated TSOL max from 260 to 220. Changed ICCSB units from mA to A. Updated Device Part Marking. Updated links and Tsol. Corrected Theta JC value on XC2C256-7TQ144. Pb-free documentation Changes to ICCSB maximum specifications in DC Electrical Characteristics table, on page 3. Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. Revision
DS094 (v2.6) October 1, 2004 Preliminary Product Specification
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